ARM: uniphier: fix DSPLL init code for LD20 SoC

Signed-off-by: Dai Okamura <[email protected]>
Signed-off-by: Masahiro Yamada <[email protected]>

diff --git a/arch/arm/mach-uniphier/clk/pll-base-ld20.c b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
index 697eb7aabf01c4889b6acce5ff79d080d23fb780..3aa42f8bfdcd9909e3aae3cc5bf8f31aeba94775 100644 (file)
--- a/arch/arm/mach-uniphier/clk/pll-base-ld20.c
+++ b/arch/arm/mach-uniphier/clk/pll-base-ld20.c
@@ -88,7 +88,7 @@ int uniphier_ld20_sscpll_set_regi(unsigned long reg_base, unsigned regi)
        if (!base)
                return -ENOMEM;
 
-       tmp = readl(base + 8);  /* SSCPLLCTRL */
+       tmp = readl(base + 8);  /* SSCPLLCTRL3 */
        tmp &= ~SC_PLLCTRL3_REGI_MASK;
        tmp |= regi << SC_PLLCTRL3_REGI_SHIFT;
        writel(tmp, base + 8);
@@ -133,9 +133,9 @@ int uniphier_ld20_dspll_init(unsigned long reg_base)
        if (!base)
                return -ENOMEM;
 
-       tmp = readl(base + 8);          /* DSPLLCTRL2 */
+       tmp = readl(base + 4);          /* DSPLLCTRL2 */
        tmp |= SC_DSPLLCTRL2_K_LD;
-       writel(tmp, base + 8);
+       writel(tmp, base + 4);
 
        iounmap(base);